CPU pinout: Difference between revisions
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* '''CPU PA20..0''': CPU physical address. PA12..0 come from the 65C02 core's A12..0 and PA20..13 from the MMU, selected by the 65C02 core's A15..13. | * '''CPU PA20..0''': CPU physical address. PA12..0 come from the 65C02 core's A12..0 and PA20..13 from the MMU, selected by the 65C02 core's A15..13. | ||
* '''K7..0''': General-purpose input (GPI) mapped to $FF:$1000-$13FF read. | * '''K7..0''': General-purpose input (GPI) mapped to $FF:$1000-$13FF read. | ||
* '''O7..0''': General-purpose output (GPO) mapped to $FF:$1000-$13FF write. | * '''O7..0''': General-purpose output (GPO) mapped to $FF:$1000-$13FF write. | ||
* '''/CER''': RAM chip enable. Asserted when accessing banks $F8-$FB. | * '''/CER''': RAM chip enable. Asserted when accessing banks $F8-$FB. | ||
* '''CE7''': HuC6270 chip enable. Asserted when accessing $FF:$0000-$03FF | * '''/CE7''': HuC6270 chip enable. Asserted when accessing $FF:$0000-$03FF | ||
* '''CEK''': HuC6260 chip enable. Asserted when accessing $FF:$0400-$07FF | * '''/CEK''': HuC6260 chip enable. Asserted when accessing $FF:$0400-$07FF | ||
* '''EAT''', '''EAT3..1''': CPU test inputs. EAT is a timer for the U-bus (HuC6280 internal peripheral bus). | * '''/EAT''', '''/EAT3..1''': CPU test inputs. EAT is a timer for the U-bus (HuC6280 internal peripheral bus). | ||
* '''HSM''': High speed mode. Asserted if the CPU is running in its 7.16 MHz mode. | * '''HSM''': High speed mode. Asserted if the CPU is running in its 7.16 MHz mode. | ||
* '''/IRQ1''': Interrupt input from the VDC. | * '''/IRQ1''': Interrupt input from the VDC. | ||
Latest revision as of 07:21, 28 August 2023
Pinout
^
/ \
/ \
/ \
CPU PA5 <- / 1 80 \ -> CPU PA6
CPU PA4 <- / 2 79 \ -> CPU PA7
CPU PA3 <- / 3 78 \ -> CPU PA8
CPU PA2 <- / 4 O 77 \ -> CPU PA9
CPU PA1 <- / 5 76 \ -- +5V (VBB)
CPU PA0 <- / 6 75 \ -- GND (VSS2)
GND (VSS1) -- / 7 74 \ -> CPU PA10
+5V (VAA) -- / 8 73 \ -> CPU PA11
n/c ?? / 9 72 \ -> CPU PA12
OSC -> / 10 71 \ -> CPU PA13
/RST -> / 11 70 \ -> CPU PA14
RDY -> / 12 69 \ -> CPU PA15
SX <- / 13 68 \ -> CPU PA16
HSM <- / 14 67 \ -> CPU PA17
+5V (VPPD) -- / 15 66 \ -> CPU PA18
GND (VSS5) -- / 16 65 \ -> CPU PA19
AUDIO LOUT <- / 17 \
AUDIO ROUT <- / 18 /
+5V AUDIO (VPPA) -- / 19 64 / -> CPU PA20
GND AUDIO (AGND) -- / 20 63 / -> CPU /WR
GND (VSSA) -- / 21 HuC6280 HUDSON 62 / -> CPU /RD
K0 -> / 22 Package QFP-80 61 / -> /CER
n/c ?? / 23 60 / -> /CE7
K1 -> / 24 59 / -> /CEK
/ 58 / -- GND (VSS3)
\ 57 / -- +5V (VCC)
K2 -> \ 25 56 / <> CPU D7
K3 -> \ 26 55 / <> CPU D6 Orientation:
K4 -> \ 27 54 / <> CPU D5 --------------------
K5 -> \ 28 53 / <> CPU D4 64 41
K6 -> \ 29 52 / <> CPU D3 | |
K7 -> \ 30 51 / <> CPU D2 .-----------.
O0 <- \ 31 50 / <> CPU D1 65-| O|-40
O1 <- \ 32 49 / <> CPU D0 | HuC6280|
O2 <- \ 33 48 / -- GND (VSS4) 80-|O HUDSON |-25
O3 <- \ 34 47 / -- +5V (VDD) '-----------'
O4 <- \ 35 46 / -> SYNC | |
O5 <- \ 36 45 / <- /NMI 01 24
O6 <- \ 37 O 44 / <- /IRQ1
O7 <- \ 38 43 / <- /IRQ2 Legend:
/EAT -> \ 39 42 / <- /EA1 ----------------------------
/EA3 -> \ 40 41 / <- /EA2 --[HuC6280]-- Power, n/a
\ / ->[HuC6280]<- HuC6280 input
\ / <-[HuC6280]-> HuC6280 output
\ / <>[HuC6280]<> Bidirectional
V ??[HuC6280]?? Unknown
Signal descriptions
- OSC: 21.4772 MHz clock input.
- SX: An inverted output of the system clock, normally not connected.
- CPU PA20..0: CPU physical address. PA12..0 come from the 65C02 core's A12..0 and PA20..13 from the MMU, selected by the 65C02 core's A15..13.
- K7..0: General-purpose input (GPI) mapped to $FF:$1000-$13FF read.
- O7..0: General-purpose output (GPO) mapped to $FF:$1000-$13FF write.
- /CER: RAM chip enable. Asserted when accessing banks $F8-$FB.
- /CE7: HuC6270 chip enable. Asserted when accessing $FF:$0000-$03FF
- /CEK: HuC6260 chip enable. Asserted when accessing $FF:$0400-$07FF
- /EAT, /EAT3..1: CPU test inputs. EAT is a timer for the U-bus (HuC6280 internal peripheral bus).
- HSM: High speed mode. Asserted if the CPU is running in its 7.16 MHz mode.
- /IRQ1: Interrupt input from the VDC.
- /IRQ2: Interrupt input from HuCards and the expansion port.
- /NMI: Non-maskable input from the expansion port.
- SYNC: Asserted during opcode fetch and deasserted otherwise (including during reset). Can be used for single-stepping execution, but is normally not connected.
- RDY: Ready. Deasserting halts the CPU until asserted again.
- /RST: Reset.
