VDC pinout

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Pinout

                                           ^
                                          / \
                                         /   \
                                        /     \
                                /CS -> / 1  80 \ <- CPU PA1
                           CPU /WR -> / 2    79 \ <- CPU PA0
                          CPU /RD -> / 3      78 \ -> /BUSY
                         CPU D15 <> / 4    O   77 \ -> /IRQ
                        CPU D14 <> / 5          76 \ -> MA15
                       CPU D13 <> / 6            75 \ -> MA14
                      CPU D12 <> / 7              74 \ -> MA13
                     CPU D11 <> / 8                73 \ -> MA12
                    CPU D10 <> / 9                  72 \ -- +5V (VDD4)
                    CPU D9 <> / 10                   71 \ -- GND (VSS4)
               GND (VSS1) -- / 11                     70 \ -> MA11
                  CPU D8 <> / 12                       69 \ -> MA10
                 CPU D7 <> / 13                         68 \ -> MA9
                CPU D6 <> / 14                           67 \ -> MA8
               CPU D5 <> / 15                             66 \ -> MA7
              CPU D4 <> / 16                               65 \ -> MA6
             CPU D3 <> / 17                                    \
        +5V (VDD1) -- / 18                                     /
           CPU D2 <> / 19                                  64 / -> MA5
          CPU D1 <> / 20                                  63 / -> MA4
         CPU D0 <> / 21          HuC6270 HUDSON          62 / -> MA3
          8/16 -> / 22          Package QFP-80          61 / -> MA2
           CK -> / 23                                  60 / -> MA1
        /RST -> / 24                                  59 / -> MA0
               /                                     58 / <> MD15
               \                                    57 / <> MD14
       /VSYN -> \ 25                               56 / <> MD13
        /HSYN -> \ 26                             55 / -- GND (VSS3)      Orientation:
          DISP <- \ 27                           54 / <> MD12             --------------------
           SPBG <- \ 28                         53 / <> MD11                 64         41
             VD7 <- \ 29                       52 / <> MD10                   |         |
              VD6 <- \ 30                     51 / <> MD9                    .-----------.
               VD5 <- \ 31                   50 / <> MD8                  65-|          O|-40
         +5V (VDD2) -- \ 32                 49 / <> MD7                      |    HuC6270|
          GND (VSS2) -- \ 33               48 / <> MD6                    80-|O  HUDSON  |-25
                  VD4 <- \ 34             47 / -- +5V (VDD3)                 '-----------'
                   VD3 <- \ 35           46 / <> MD5                          |         |
                    VD2 <- \ 36         45 / <> MD4                          01         24
                     VD1 <- \ 37   O   44 / <> MD3
                      VD0 <- \ 38     43 / <> MD2                         Legend: 
                      /MWR <- \ 39   42 / <> MD1                          ----------------------------
                       /MRD <- \ 40 41 / <> MD0                           --[HuC6270]-- Power, n/a  
                                \     /                                   ->[HuC6270]<- HuC6270 input 
                                 \   /                                    <-[HuC6270]-> HuC6270 output 
                                  \ /                                     <>[HuC6270]<> Bidirectional
                                   V

Signal descriptions

  • CK: Input clock from the VEC, configured by the CPU.
  • /CS: Chip select. Connected to CPU /CE7, selecting the VDC when writing to $FF:$0000-$03FF.
  • 8/16: Controls CPU data bus width. This is connected to +5V.
  • CPU D15..8: The upper half of the CPU data bus when operating in 16-bit mode. However, the PC Engine uses 8-bit mode exclusively, so these are not connected.
  • /IRQ: Interrupt output to the CPU.
  • /BUSY: Asserted during CPU writes until the VDC is able to service the write. Connected to CPU RDY.
  • MA15..0: The VDC VRAM address bus.
  • MD15..0: The VDC VRAM data bus.
  • /MRD, /MWR: Indicates read and write on the VDC VRAM bus.
  • SPBG, VD7..0: The 9-bit color index output to the VCE. SPBG acts as bit 8. High for sprites and low for backgrounds.
  • /HSYN, /VSYN: Horizontal and vertical sync from the VCE, to which the VDC synchronizes its video output.
  • DISP: A test output indicating different regions of the picture, configured through control register (CR, register $05) and normally not connected:
    • CR.9..8 = 00: DISP - asserted during active pixels.
    • CR.9..8 = 01: BURST - deasserted during color burst.
    • CR.9..8 = 10: INTHSYNC - outputs the internal horizontal sync signal.
    • CR.9..8 = 11: (unused)