VCE pinout
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Pinout
^
/ \
/ \
/ \
+5V (D) -- / 1 80 \ <- 8/16
OSC -> / 2 79 \ <- /CS
GND (D) -- / 3 78 \ <- CPU /RD
CPU D8 <> / 4 O 77 \ <- CPU /WR
CPU D7 <> / 5 76 \ <- CPU PA2
CPU D6 <> / 6 75 \ <- CPU PA1
CPU D5 <> / 7 74 \ <- CPU PA0
CPU D4 <> / 8 73 \ -> CK
CPU D3 <> / 9 72 \ -> /VSYN
CPU D2 <> / 10 71 \ -> /HSYN
CPU D1 <> / 11 70 \ <- VD8
CPU D0 <> / 12 69 \ <- VD7
+5V (D) -- / 13 68 \ <- VD6
GND (D) -- / 14 67 \ <- VD5
GND (D) -- / 15 66 \ <- VD4
+5V (D) -- / 16 65 \ <- VD3
BRT- -> / 17 \
BRTC <> / 18 /
GND (A) -- / 19 64 / <- VD2
BURS <- / 20 63 / <- VD1
+5V (A) -- / 21 HuC6260 HUDSON 62 / <- VD0
BRT+ -> / 22 Package QFP-80 61 / <- SEL
B-Y- <> / 23 60 / ?? TEST3
B-YC <> / 24 59 / <- TEST2 (YUV HI/LO)
/ 58 / <- TEST1 (PAL/YUV)
\ 57 / -- +5V (D)
GND (A) -- \ 25 56 / -- GND (D) Orientation:
B-Y <- \ 26 55 / -- GND (D) --------------------
+5V (A) -- \ 27 54 / -- +5V (D) 64 41
B-Y+ -> \ 28 53 / -- +5V (D) | |
GND (A) -- \ 29 52 / <- RGB+ .-----------.
R-Y- <> \ 30 51 / -> B 65-| O|-40
R-YC <> \ 31 50 / -- +5V (A) | HuC6260|
GND (A) -- \ 32 49 / -> R 80-|O HUDSON |-25
R-Y <- \ 33 48 / -- GND (A) '-----------'
+5V (A) -- \ 34 47 / -> G | |
R-Y+ -> \ 35 46 / <> RGB- 01 24
+5V (A) -- \ 36 45 / <- SYN+
Y- <> \ 37 O 44 / -> SYNC Legend:
YC <> \ 38 43 / <> SYN- ----------------------------
GND (A) -- \ 39 42 / <- Y+ --[HuC6260]-- Power, n/a
Y <- \ 40 41 / -- +5V (A) ->[HuC6260]<- HuC6260 input
\ / <-[HuC6260]-> HuC6260 output
\ / <>[HuC6260]<> Bidirectional
\ / ??[HuC6260]?? Unknown
V
Signal descriptions
- +5V (A), GND (A): Power for analog signals.
- +5V (D), GND (D): Power for digital signals.
- OSC: 21.4772 MHz clock input.
- CK: Output clock for the VDC, configured by the CPU.
- /CS: Chip select. Connected to CPU CEK, selecting the VDC when writing to $FF:$0400-$07FF.
- 8/16: Controls CPU data bus width. This is connected to +5V (8-bit mode).
- CPU D8: Used in 16-bit mode. However, the PC-Engine uses 8-bit mode exclusively, so this is not connected.
- VD8..VD0: 9-bit color input from the VDC. VD8 is connected to the VDC's SPBG output.
- /HSYN, /VSYN: Horizontal and vertical sync for the VDC, to which the VDC synchronizes its video output.
- SEL: 'Output Control' or 'Video Select'. Deasserting makes /HSYN, /VSYN, and CK go high impedance, freezing output from the VDC, but the VCE still draws VD8..0 input as normal. Connected to the expansion port (along with /HSYN, /VSYN, and CK), but normally floating externally.
- TEST1 (PAL/YUV): When grounded, reading palette RAM returns data from the YUV ROM, instead. The YUV ROM is indexed using the value at the palette RAM address being read by the CPU. This pin is normally not connected.[1]
- TEST2 (YUV HI/LO): Controls which half of the 15-bit YUV value is returned to the CPU when reading from YUV ROM. When reading the high byte, bit 7 is always 0. This pin is normally not connected.[1]
- TEST3: This appears to have a function, but its behavior is unknown. Normally not connected.
Note: Pins appear to be pulled up internally, so not connected pins are high.
