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- 13:40, 28 January 2025 EXT BUS pinout (hist | edit) [2,346 bytes] Lidnariq (talk | contribs) (Created page with "On the back of PC Engine, CoreGrafx, CoreGrafx2, but *not* Shuttle, 3x23 0.1" pin header From perspective of someone looking into the back of the console, holding the AV or RF port up, power jack down, and card slot away from you: {| class="wikitable" |AudioL || AudioC || AudioR |- | +5A || K7 || 0VAG |- |CESEL || HSM || /CARD |- |A18 || /WR || /CEK |- |A14 || /NMI || A17 |- |A9 || A8 || A13 |- |A10 || /RD || A11 |- |D6 || D7 || GND |- |DCK || D4 || D5 |- |/VSYNC || D...")
- 09:05, 29 August 2023 VCE pinout (hist | edit) [5,411 bytes] Fiskbit (talk | contribs) (Adds VCE pinout. Still need to figure out how to document the analog power connections.)
- 15:43, 28 August 2023 Timing (hist | edit) [496 bytes] Asie (talk | contribs) (Created page with "The (NTSC) PC Engine is clocked with a master clock equal to six times the NTSC color burst (<code>315/88</code> MHz), or approximately 21.47727 MHz. This is divided into the following clocks: * CPU "high" clock speed = master clock / 3 (approx. 7.15909 MHz), * CPU "low" clock speed = master clock / 12 (approx. 1.78978 MHz), * Timer speed = master clock / 3072 (approx. 6.991 KHz), * VCE pixel clocks: ** "10MHz" = master clock / 2, ** "7MHz" = master clock / 3, ** "5MHz...")
- 13:34, 28 August 2023 CPU addresses (hist | edit) [1,065 bytes] Fiskbit (talk | contribs) (Adds explanation of CPU addresses and terms.)
- 13:25, 28 August 2023 CPU memory map (hist | edit) [2,509 bytes] Fiskbit (talk | contribs) (Adds initial CPU memory map.)
- 07:50, 16 August 2023 VDC pinout (hist | edit) [5,062 bytes] Fiskbit (talk | contribs) (Adds VDC pinout.)
- 07:40, 16 August 2023 HuCard pinout (hist | edit) [2,117 bytes] Fiskbit (talk | contribs) (Adds HuCard pinout.)
- 07:31, 16 August 2023 CPU pinout (hist | edit) [5,140 bytes] Fiskbit (talk | contribs) (Adds CPU pinout.)
